1. Field of the Invention
The present invention relates to a process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure.
More specifically, the invention relates to a process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps:
defining on a same semiconductor substrate respective active areas for said byte selection transistor, for said floating gate transistor and for said selection transistor split by portions of insulating layer;
depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer.
The invention relates also to a circuit structure comprising a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, associated to a circuitry comprising high and low voltage transistors, each memory cell comprising a floating gate transistor and a selection transistor, said rows being interrupted by at least a couple of byte selection transistors, said transistors being manufactured in respective active areas delimited by portions of insulating layer.
The invention relates particularly, but not exclusively, to a process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and the following description is made with reference to this field of application for convenience of illustration only.
2. Description of the Related Art
As it is well known, a matrix of non volatile memory cells comprises a plurality of non volatile memory cells integrated on a semiconductor material substrate arranged in rows and columns.
Each non volatile cell is formed by a floating gate transistor and by a selection transistor. The floating gate region of the floating gate transistor is formed on a semiconductor substrate and split therefrom by a thin gate oxide layer. A control gate region is capacitively coupled to the floating gate region by means of a dielectric layer and metallic electrodes are provided to contact the drain, source terminals and the control gate region in order to apply predetermined voltage values to the memory cell. The selection transistor is instead manufactured by means of a traditional MOS transistor comprising a gate region formed on a semiconductor substrate and split therefrom by a thin gate oxide layer. Source and drain regions are integrated in the substrate at the gate region ends.
The cells belonging to a same word line have a common electric line driving the respective control gates by means of the byte selection transistor, while the cells belonging to a same bit line have common drain terminals.
The matrix of memory cells is organized in turn in bytes, each one comprising 8 bits (or multiples). Each byte can be selected from outside the matrix by means of a byte transistor located in correspondence with each byte.
A first known technical solution to form a matrix of non volatile cells provides the use of two different masks for manufacturing the selection and byte transistors having a gate region with a single polysilicon level, while the gate region of the floating gate transistor is manufactured with a double polysilicon layer.
Therefore, in the matrix portion wherein the selection and byte transistors are manufactured a removal step of one of the two polysilicon layers used to form the double polysilicon layer must be performed.
Although advantageous under many aspects, this first solution has several drawbacks. In fact, the removal step of a polysilicon layer from the active areas of the selection and byte transistors of one of the two polysilicon layers can degrade the electric features of these devices. Moreover the resulting structure comprises the series of devices with different heights which make the cleaning steps provided in the traditional process flow particularly difficult.